CMOS Integration. • Devices are built into a common p-type substrate (wafer). • Shallow Trench Isolation (STI) provides electrical isolation between devices.
STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use ...
由 P Sallagoity 著作 · 1998 · 被引用 30 次 — This paper presents an improved STI process which has been developed for a 0.18 μm CMOS technology. A new CVD silicon oxide deposition process achieves ...